Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are susceptible to damage when exposed to an electrostatic discharge (ESD) event. An ESD event may occur, for example, when a user who has accumulated electrostatic charge picks up a CMOS IC. The accumulated charge may cause an instantaneous voltage of a few thousand volts to appear across terminals of the IC. This voltage is large enough to cause permanent damage to CMOS transistors, such as by rupturing the gates of the transistors. Thereafter, the CMOS IC cannot function properly.
In order to prevent the damage caused by an ESD event, CMOS IC designers include ESD protection circuits adjacent to input and/or output IC terminals. These circuits typically include diodes to discharge a large voltage appearing on a signal terminal into a power supply terminal. Designers also typically include active power supply voltage rail clamps that become active to quickly dissipate a voltage between the power and ground power supply voltage terminals built up during an ESD event.
Increasingly integrated circuits operate in multiple power domains. For example, it may be desirable to use multiple power domains to allow for different voltages for input/output buffers dedicated to each domain. However support for multiple power domains complicates the ESD protection task because now different discharge paths are possible. Furthermore when I/O buffers for one power domain are interspersed with I/O buffers for another power domain their ESD protection will require substantial layout area.